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66 lines
3.0 KiB
66 lines
3.0 KiB
/*
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* clk.h
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*
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* Copyright (c) 2014 Jeremy Garff <jer @ jers.net>
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice, this list
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* of conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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* 3. Neither the name of the owner nor the names of its contributors may be used to endorse
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* or promote products derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef __CLK_H__
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#define __CLK_H__
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typedef struct {
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uint32_t ctl;
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#define CM_CLK_CTL_PASSWD (0x5a << 24)
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#define CM_CLK_CTL_MASH(val) ((val & 0x3) << 9)
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#define CM_CLK_CTL_FLIP (1 << 8)
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#define CM_CLK_CTL_BUSY (1 << 7)
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#define CM_CLK_CTL_KILL (1 << 5)
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#define CM_CLK_CTL_ENAB (1 << 4)
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#define CM_CLK_CTL_SRC_GND (0 << 0)
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#define CM_CLK_CTL_SRC_OSC (1 << 0)
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#define CM_CLK_CTL_SRC_TSTDBG0 (2 << 0)
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#define CM_CLK_CTL_SRC_TSTDBG1 (3 << 0)
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#define CM_CLK_CTL_SRC_PLLA (4 << 0)
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#define CM_CLK_CTL_SRC_PLLC (5 << 0)
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#define CM_CLK_CTL_SRC_PLLD (6 << 0)
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#define CM_CLK_CTL_SRC_HDMIAUX (7 << 0)
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uint32_t div;
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#define CM_CLK_DIV_PASSWD (0x5a << 24)
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#define CM_CLK_DIV_DIVI(val) ((val & 0xfff) << 12)
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#define CM_CLK_DIV_DIVF(val) ((val & 0xfff) << 0)
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} __attribute__((packed, aligned(4))) cm_clk_t;
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/*
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* PWM and PCM clock offsets from https://www.scribd.com/doc/127599939/BCM2835-Audio-clocks
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*
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*/
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#define CM_PCM_OFFSET (0x00101098)
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#define CM_PWM_OFFSET (0x001010a0)
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#endif /* __CLK_H__ */
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