Routed most of the VCA. Corrected circuit mistakes

master
Davide Bongiovanni 3 years ago
parent 6b0597056b
commit 8b3d065726

@ -16,23 +16,23 @@ $EndDescr
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L Amplifier_Operational:LM13700 U3
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$Comp
L Amplifier_Operational:LM13700 U3
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@ -140,36 +140,25 @@ Wire Wire Line
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F 3 "~" H 3300 1450 50 0001 C CNN
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$Comp
L Device:R R10
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F 3 "~" H 3400 1650 50 0001 C CNN
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F 2 "Resistor_SMD:R_0603_1608Metric" V 3230 1650 50 0001 C CNN
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 3050 1650
Connection ~ 9400 3850
Wire Wire Line
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@ -187,49 +176,44 @@ $EndComp
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Wire Wire Line
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F 3 "~" H 2800 1450 50 0001 C CNN
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F 0 "R5" V 3100 1050 50 0000 C CNN
F 1 "300k" V 3200 1100 50 0000 C CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 3230 1100 50 0001 C CNN
F 3 "~" H 3300 1100 50 0001 C CNN
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Wire Wire Line
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F 3 "~" H 2400 1450 50 0001 C CNN
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Wire Wire Line
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Wire Wire Line
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@ -523,67 +507,51 @@ Wire Wire Line
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F 3 "~" H 3400 4950 50 0001 C CNN
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$Comp
L Device:R R12
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F 3 "~" H 3400 5150 50 0001 C CNN
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F 3 "~" H 3300 5150 50 0001 C CNN
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Wire Wire Line
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Wire Wire Line
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$Comp
L Device:R R7
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Wire Wire Line
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@ -1001,4 +969,44 @@ F 3 "http://www.ti.com/lit/ds/symlink/tl081.pdf" H 8750 3750 50 0001 C CNN
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 3550 1450
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Connection ~ 3050 5150
Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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@ -16,23 +16,23 @@ $EndDescr
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L Amplifier_Operational:LM13700 U3
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F 2 "Package_SO:SOIC-16_3.9x9.9mm_P1.27mm" H 4050 1575 50 0001 C CNN
F 3 "http://www.ti.com/lit/ds/symlink/lm13700.pdf" H 4050 1575 50 0001 C CNN
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$Comp
@ -140,36 +140,25 @@ Wire Wire Line
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F 3 "~" H 3400 1450 50 0001 C CNN
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F 3 "~" H 3400 1650 50 0001 C CNN
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Wire Wire Line
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Connection ~ 3050 1650
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Wire Wire Line
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@ -187,21 +176,21 @@ $EndComp
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Wire Wire Line
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L Device:R R5
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$Comp
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Wire Wire Line
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Wire Wire Line
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File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

@ -1,29 +1,10 @@
update=22/05/2015 07:44:53
update=2021-01-27 17:32:54
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
@ -31,3 +12,230 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.3
ViaDiameter1=0.8
ViaDrill1=0.4
ViaDiameter2=0.6
ViaDrill2=0.35
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

@ -785,10 +785,10 @@ Wire Wire Line
Wire Wire Line
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$Comp
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$EndComp
$Comp
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F 3 "" H 7850 3850 50 0001 C CNN

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